Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)
説明
Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, C/sub G,eff/ it is shown that the power and delay of CMOS digital circuit can be estimated accurately. C/sub G,eff/ is a strong function of V/sub TH//V/sub DD/ and V/sub TH//V/sub DD/ tends to increase in low-voltage region. Hence, the effective capacitance relative to oxide capacitance, C/sub OX/, is decreasing in low-voltage, low-power designs. Therefore, considering C/sub G,eff/ in accurate power and delay estimation becomes more important in the future.
収録刊行物
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- Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00
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Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00 228-230, 2000-01-01
ACM Press