Concurrent logic and layout design system for high performance LSIs
説明
This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.
収録刊行物
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- Proceedings of the IEEE 1995 Custom Integrated Circuits Conference
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Proceedings of the IEEE 1995 Custom Integrated Circuits Conference 465-468, 2002-11-19
IEEE