Future trends in BiCMOS technology

BiCMOS provides CMOS power and densities at Bipolar speeds. At a given technology level, BiCMOS out performs CMOS by a factor of 1.5 - 2.OX. A 0.8? BiCMOS technology exceeds the performance of a sub-0.5?m CMOS technology. This has been demonstrated in applications ranging from SRAMs to microprocessors. The main disadvantage of BiCMOS is process complexity, which results in a 1.1-1.3X packaged chip cost. Now that BiCMOS has been demonstrated at 0.5?m, the challenge has shifted from process and technology to circuits and systems. The role of BiCMOS in a reduced power supply environment is still controversial. Two approaches are being taken to resolve the speed degradation of the conventional BiCMOS buffer at 3.3V. On-chip voltage regulation is being used to operate sub-0.5?m CMOS at lower fields, while maintaining the I/0 at standard 5V levels. The second approach replaces conventional BiCMOS buffers with new logic gates capable of operating below 3V. It follows that BiCMOS technology will extend the use of TTL & ECL interfaces into the deep sub-micron regime. Both digital and digital-analog systems will exploit these advanced BiCMOS technologies.