A high-level synthesis approach to partial scan design based on acyclic structure
説明
This paper presents a high-level synthesis method for testable data paths with partial scan design based on acyclic structure. For a given scheduled data flow graph, we propose a heuristic method of operational unit binding and register binding to minimize the number of scan registers for acyclic structure without sacrifice of area overhead.
収録刊行物
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- Proceedings Eighth Asian Test Symposium (ATS'99)
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Proceedings Eighth Asian Test Symposium (ATS'99) 309-314, 2003-01-20
IEEE Comput. Soc