A CMOS flash TDC with 0.84 – 1.3 ps resolution using standard cells

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This paper proposes a new flash time-to-digital converter (TDC) design, which incorporates deterministic, variable delay into the decision elements. These are implemented with cross-coupled NAND standard cells of variable transistor widths. Both experiment and simulation are used to validate this new design, which provides variable time-difference ranges by controlling the input slew rate. It is also possible to use the proposed flash TDC as a soft macro.

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