A study of a high bandwidth and low latency interconnection network in PIE64
説明
PIE64 is a parallel inference machine. The goal is fast execution of large-scale knowledge processing. Generally speaking, an interconnection network (IN) is one of the keys to designing a parallel machine and affects a total system architecture. The IN of PIE64 is designed with the aim of maximizing its performance. A discussion is presented of the IN suitable for PIE64, and an IN with circuit switching, nonbuffering, multistage, dynamic load balancing support, and duplicated network is proposed. Its hardware implementation is considered, and the assembling process is described. Electrical characteristics are also described. >
収録刊行物
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- [1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings
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[1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings 5-8, 2002-12-09
IEEE