Multiple-valued arithmetic integrated circuits based on 1.5 V-supply dual-rail source-coupled logic
説明
This paper presents a new multiple-valued current-mode MOS integrated circuit for high-speed arithmetic systems with a low supply voltage. The use of a multiple-valued source-coupled logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the switching delay of the circuit can be reduced at a low supply voltage. As an application to arithmetic systems, we demonstrate that a 1.5 V-supply 200 MHz 54/spl times/54-bit pipelined multiplier using the proposed circuits can be designed with a 0.8-/spl mu/m standard CMOS technology.
収録刊行物
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- Proceedings 25th International Symposium on Multiple-Valued Logic
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Proceedings 25th International Symposium on Multiple-Valued Logic 64-69, 2002-11-19
IEEE Comput. Soc. Press