Diagnosis of Delay Faults Considering Hazards
説明
It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in sub micron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest transition times. It can deal with hazard signals more accurately than conventional methods. The proposed method uses a fault dictionary to deduce candidate faults which sufficiently explain the output responses of a circuit under diagnosis.
収録刊行物
-
- 2015 IEEE Computer Society Annual Symposium on VLSI
-
2015 IEEE Computer Society Annual Symposium on VLSI 503-508, 2015-07-01
IEEE
