Counterdoped well structure for scaled CMOS
説明
A counterdoped well structure has been developed, and is characterized by partial compensation of the boron doped region by subsequent phosphorous doping in the case of a p-type well. The sheet resistance of the counterdoped p-well is less than 4 KΩ/□ even for 5 \micro m well depth, which is about half of that for the conventional well, while effective surface concentration is kept around 5 \times 10^{15} cm-3. Holding current of parasitic thyristors in counterdoped test devices is significantly larger than for those made with the conventional p-well, in agreement with simulation. No abnormal characteristics were observed either test devices or an LSI memory fabricated using the counterdoped p-well. The counterdoped well realizes reduced latch-up susceptibility without sacrificing device performance, thus this approach is promising for scaled CMOS below 2 \micro m.
収録刊行物
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- 1982 International Electron Devices Meeting
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1982 International Electron Devices Meeting 470-473, 1982-01-01
IRE