A very fast three-mode retiming PLL with low jitter and wide operating margin
説明
The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 /spl mu/m bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error.
収録刊行物
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- Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems
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Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems 340-345, 2002-12-17
IEEE