Modeling the overshooting effect in the submicrom CMOS inverters
説明
The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of. the input-to-output coupling, capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with SPICE simulations.
収録刊行物
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- Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005.
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Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005. 2 1191-1195, 2005-08-16
IEEE
