Development of Reconfiguration unit for General Purpose Microcomputer with Dynamic Partial Reconfiguration

Video image processing is an essential feature in embedded devices. In order to facilitate the development of video image processing hardware, we are developing the generic verification environment. This is able to install in any of the FPGA and has the standard circuits which interface to the cameras, memories, displays and a host PC around the video image processing hardware. The current verification environment has the single frame buffer for the display. If the video image processing hardware in the verification environment makes a large processing load, flickering on the display is preventing visual confirmation. In this paper, we improve the display unit by introducing a double buffer in the verification environment. In the experiment, the effect of the double buffer is evaluated by compared to the single buffer. The result shows that the double buffer is able to eliminate the flicker of the video image. Resource utilization of the verification environment didn’t change significantly. That is, the circuit scale of the verification environment is maintained even though the several circuits arbitrating the double buffer between the video processing hardware and the display controller are introduced.