説明
This paper presents a method for thread partitioning for a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, and then converted into synthesizable behavioral VHDL models. The proposed method attempts to find a partitioning of a given system description into threads that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.
収録刊行物
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- Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00
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Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 303-308, 2000-01-01
ACM Press