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A fault-tolerant architecture for nanoe ectronic signa processing
Bibliographic Information
- Published
- 2005-04-01
- DOI
-
- 10.1109/nano.2004.1392428
- Publisher
- IEEE
Description
A fault-tolerant system architecture is proposed for digital signal processing with quantum devices which make transient errors. Two techniques are employed in the proposed architecture. Firstly, there exists no circuit block to control system operation sequence. Every circuit modules in the system autonomously repeat simple operation at each clock cycle. This structure prevents system failures. Secondly, pulse density modulated single-bit data whose average represents signal level is the data form for the system. Unlike multi-bit binary data, a few bit-errors do not make data haphazard but merely let data lower in accuracy. Computer simulation of a digital filter based on the architecture demonstrated the effectiveness of these techniques.
Journal
-
- 4th IEEE Conference on Nanotechnology, 2004.
-
4th IEEE Conference on Nanotechnology, 2004. 586-588, 2005-04-01
IEEE