Effect of Parallel Processing on a Generic SoC Platform Using DPR
説明
Electronic products become more multifunctional and diversified. Thus, the SoC is needed to be larger and more diversified, be smaller and more high-perfomance. To satisfy these demands, enormous effort and cost of development are needed. However, such enormous effort and cost increase the cost of products. Therefore, a generic SoC platform which is able to be used in various applications is needed to reduce the burden of developers and cost. So far, the Dynamic partial reconfiguration (DPR) of hardware is one of the candidates to tackle such problem mentioned above. We have proposed a generic SoC platform, dynamic partial reconfiguration platform (DyREP), which uses the DPR nature. In this paper, we confirm an effect of parallel processing on DyREP, where the multiple reconfigurable modules can be executed simultaneously. Consequently, we attempt to clarify that the parallel processing on the DyREP can improve the performance.
収録刊行物
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- The Proceedings of the 1st International Conference on Industrial Application Engineering 2013
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The Proceedings of the 1st International Conference on Industrial Application Engineering 2013 158-161, 2013-03-27
The Institute of Industrial Applications Engineers
