説明
We designed a cell-network-based video segmentation test-chip in 0.35/spl mu/m CMOS technology including a power reduction technique which activates only boundary cells of currently grown regions. The effectiveness of the proposed technique is confirmed by measurement results for a 41/spl times/33-sized cell-network, with 23/spl mu/sec segmentation time (avg.) and 45.8mW power-dissipation (avg.) at 10MHz clock frequency.
収録刊行物
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- Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05
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Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05 13-, 2005-01-01
ACM Press
