Impact on delay due to random telegraph noise under low voltage operation in logic circuits
説明
Recently, reliability of an advanced LSI becomes a serious issue because of the variability associated with the technology scaling. In particular, Random Telegraph Noise (RTN) has attracted much attention as a temporal variation that has been enlarged with the scaling. Recently, Intel demonstrated a micro processor that can operate over a wide voltage range from 0.28 V to 1.2 V, targeting nearthreshold computing that brings the promise of an order of magnitude improvement in energy efficiency [1]. However, such an aggressive voltage scaling may not result in a stable operation of conventional logic circuits. In nearthreshold operation, a slight fluctuation in the threshold voltage (∆Vth) such as induced by RTN, may lead to a serious delay increase that will cause malfuction of the circuit operation. The purpose of this paper is to evaluate and issue an alert the impact of RTN on circuit delay fluctuation under low voltage operation.
収録刊行物
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- Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
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Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials 2012-01-01
The Japan Society of Applied Physics
