Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints
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説明
This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints
収録刊行物
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- 25th IEEE VLSI Test Symmposium (VTS'07)
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25th IEEE VLSI Test Symmposium (VTS'07) 369-374, 2007-05-01
IEEE