- 【Updated on May 12, 2025】 Integration of CiNii Dissertations and CiNii Books into CiNii Research
- Trial version of CiNii Research Knowledge Graph Search feature is available on CiNii Labs
- Suspension and deletion of data provided by Nikkei BP
- Regarding the recording of “Research Data” and “Evidence Data”
Low-jitter PLL by interpolate compensation
Description
In order to reduce jitters, vital characteristics in some PLL applications, a PLL with compensator and interpolative loop is proposed. This PLL improves the problem that conventional PLL cannot detect jitters at the time other than the reference input. AS a result, it reduces jitters as frequency synthesizers with high multiplication ratios. We tailored the circuit to improve responsiveness, as well. The effectiveness is verified on a prototype implemented in a Cyclone FPGA, and experiments as a mutiply-by-50 synthesizer results in 30-fold reduction in two jitter measures.
Journal
-
- APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
-
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems 1078-1081, 2008-11-01
IEEE
