3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs
説明
The authors propose and discuss sense amplifiers suitable for low voltage operation. Compared with a conventional current sensing scheme, the hierarchical voltage sensing scheme reduces sensing delay by 39% and improves functional minimum voltage to 1.8 V, which is sufficiently low for a 3.3-V static RAM (SRAM). High-speed sensing techniques for 4-Mb VLSI SRAMs and beyond, and performance of a 9-ns, 4-Mb transistor-transistor-logic input/output SRAM implementing one of these sense amplifiers, are also presented. >
収録刊行物
-
- Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting
-
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting 182-185, 2003-01-02
IEEE