1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology
説明
In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.
収録刊行物
-
- 2013 International Semiconductor Conference Dresden - Grenoble (ISCDG)
-
2013 International Semiconductor Conference Dresden - Grenoble (ISCDG) 1-4, 2013-09-01
IEEE
