Steady-state error reduction by digital offset control for dc-to-dc converters

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説明

This paper presents a novel algorithm of a digital control that improves a steady-state error of a dc-to-dc switching converter. Instead of the conventional Integral control, the offset control is employed in which the base-duty-cycle of Pulse Width Modulation (PWM) is updated at constant intervals so that the error of the output voltage might become small. The principle of the proposed algorithm is described in detail. The implementation of the algorithm is very simple and the code size becomes small that yield the shortest execute time. Characteristics of the proposed controller are examined, and it is found that the controller has the same characteristics as the conventional integral control. As a result, the steady-state error has been reduced to almost zero.

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