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A probabilistic neural network hardware system using a learning-parameter parallel architecture
Description
A novel PNN (Probabilistic Neural Networks) hardware architecture called 'Sigma Parallel Architecture' (SPA) is proposed. Different values of the network parameter are calculated in parallel in the SPA and it speeds up the PNN learning as well as recognition overcoming the difficulty in the VLSI implementation. The hardware prototype is developed using FPGA chips and it shows a high speed leaning of about 10 seconds that satisfies the requirements in the real world image recognition tasks.
Journal
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- Proceedings of the 2002 International Joint Conference on Neural Networks. IJCNN'02 (Cat. No.02CH37290)
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Proceedings of the 2002 International Joint Conference on Neural Networks. IJCNN'02 (Cat. No.02CH37290) 2270-2275, 2003-06-25
IEEE
