Reuse of VLSI layout topology by parametric BSG
説明
In reuse of a VLSI layout design, we first determine the information to abstract from a given design, and then prepare a data structure to store it. Since a further optimization is required in the new environment, the data structure must be flexible to accept a change in the data. In this paper, the floorplan of a given layout is focused on. It is characterized by a topological property, called the seg-based 4-direction. The parametric BSG (PBSG) is proposed as the data structure. An elegant procedure to map the seg-based 4-direction into PBSG of minimum size is given. Merits of using PBSG in reuse are discussed.
収録刊行物
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- IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394)
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IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394) 817-820, 2002-11-11
IEEE