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Digital phase-locked loop with wide lock-in range using fractional divider
Description
The authors propose a novel type of digital phase-locked loop (DPLL) with both a wide initial lock-in range and a fast initial acquisition time. In this DPLL, by using a fractional divider, it is possible for an initial fixed clock to be made as the adapting free-running frequency which is dependent on the input frequency. Therefore, one can obtain a wide initial lock-in range. Furthermore, removing the frequency offset by a fractional divider and resetting the divider, this system has a fast initial acquisition time of only 16 cycles of input. The properties of the proposed DPLL are investigated by experiments and theoretical analysis, and they are compared with those of the conventional DPLL. The results show that the proposed DPLL performs well. >
Journal
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- Proceedings of IEEE Pacific Rim Conference on Communications Computers and Signal Processing
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Proceedings of IEEE Pacific Rim Conference on Communications Computers and Signal Processing 2 431-434, 2002-12-30
IEEE
