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A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processing
Description
New reconfigurable accelerator architecture suitable for the intelligent image processing is proposed. Not only reconfigurable processing-unit blocks, but also smart data-transfer subsystems which consist of multistage interconnection networks and special buffers are implemented. The subsystem can supply any combinations of 8 /spl times/ 8 local image data simultaneously to the arbitrary processing units. The processing-unit block consists of arrays of arithmetic units which can be reconfigured as parallel adders/subtracters or multipliers with various precision. The peak performance of this accelerator is 204BOPS which is sufficient for the wavelet transforms in the real-time intelligent image-processing applications.
Journal
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- Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
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Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921) 429-432, 2005-03-21
IEEE
