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Assignment-space exploration approach to testable data-path synthesis for minimizing partial scan registers
Description
In this paper, we present an assignment-driven approach to data-path synthesis for area-efficient partial scan testability. The method basically adopts branch-and-bound strategy for exploring assignment solution space as a backbone task, and the lower bound estimates of the scheduling length, the number of scan registers and area are used for pruning. Algorithms for lower bound estimation of the number of scan registers and selection of scan registers as a leaf task are mainly demonstrated in this paper, while the assignment-driven scheduling is relegated to a previous paper.
Journal
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- IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394)
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IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394) 540-543, 2002-11-11
IEEE