GAA: a VLSI genetic algorithm accelerator with on-the-fly adaptation of crossover operators
説明
This paper describes a VLSI implementation of a genetic algorithm, called the Genetic Algorithm Accelerator (GAA) chip. Genetic algorithms (GAs) are widely used to solve complex optimization problems, and many variations of GAs have been proposed including several kinds of crossover operations. However, there have been few works, in which more than one crossover operators were used in a GA implementation to draw out the maximum capability of GAs. The authors have proposed an adaptive strategy, which selects a crossover operator to be used not in advance but dynamically during the algorithm execution. The GAA chip is a VLSI implementation of a GA with this adaptive strategy for selecting crossover operators. Hardware implementation of GA makes it possible to reduce the computation time drastically. The GAA chip has been designed with the Verilog HDL and simulated with some benchmark functions. According to the simulation, the GAA chip will finish the computation of one generation in less than 0.12 ms when the population size is 64. The chip has been fabricated with the CMOS 0.5 /spl mu/m standard cell technology.
収録刊行物
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- ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
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ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) 2 268-271, 2002-11-27
IEEE