High speed transport processor for broad-band burst transport system

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A description is given of the design of a high-speed transport processor (TP) that provides a basic virtual digital cross-connect capability in broadband burst-transport nodes. The TP has a routing function to transfer bursts arriving at an input port to their designated output port, and a scheduling function, to resolve contention when multiple bursts are simultaneously designated for one output port. The proposed architecture uses input queuing to avoid contention at output ports, scheduling control between input and output ports in a distributed manner, and separately implemented routing and scheduling functions. The performance of the TP under two typical traffic patterns is evaluated by computer simulations. This architecture overcomes the head-of-line effect, which limits input queuing throughput. It also reduces necessary buffer capacity and circuit operation speed, and has a short delay time. An experiment TP is shown to have a throughput of 1.6 Gb/s. >

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