Formal verification of self-testing properties of combinational circuits
説明
This paper proposes a method of formal verification of self-testing (ST) property of combinational circuits using logic function manipulation. In this method we show that the problem of verification of ST property can be transformed to satisfiability problem of a decision function formed from characteristic functions of the circuit's output code words. Then the problem can be resolved using binary decision diagrams (BDD) efficiently. Experimental results show the effectiveness of the proposed method.
収録刊行物
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- Proceedings of the Fifth Asian Test Symposium (ATS'96)
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Proceedings of the Fifth Asian Test Symposium (ATS'96) 119-122, 2002-12-23
IEEE Comput. Soc. Press