Sub-path delay estimation for reconvergent path
説明
In this paper, we propose a sub-path delay estimation method for reconvergent paths. In recent years, as the fabrication process becomes finer, the process variation becomes much critical issue. Especially, the consideration of the timing error becomes much necessary. To solve the timing error, a post-silicon clock tuning is promising. To refine the timing yield, the high precision of the estimation of variation is important in the post-silicon clock tuning. In this paper, we propose the estimation for the reconvergent path with path-delay test. The efficiency is confirmed empirically.
収録刊行物
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- 2012 IEEE Asia Pacific Conference on Circuits and Systems
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2012 IEEE Asia Pacific Conference on Circuits and Systems 675-678, 2012-12-01
IEEE
