LUT-based FPGA technology mapping using permissible functions
説明
In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.
収録刊行物
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- Proceedings of 9th International Conference on VLSI Design
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Proceedings of 9th International Conference on VLSI Design 215-218, 2002-12-23
IEEE Comput. Soc. Press