A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

Masahiko Yoshimoto, Junichi Miyakoshi, Koji Hamano, Masayuki Miyama, Yuichiro Murachi, Tetsuro Matsuno

doi:10.1109/vlsic.2005.1469369

Description

This paper describes a 95 mW MPEG2 [email protected] motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 1920 × [email protected] fps resolution video. The search range is ±128 × ±64 pixels. The ME core integrates 2.25 M transistors in 3.1 mm × 3.1 mm using 0.18-micron technology.

Journal

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A 3492-3499, 2005-07-27

Institute of Electronics, Information and Communications Engineers (IEICE)

Details 詳細情報について

CRID: 1873398393039778944

DOI: 10.1093/ietfec/e88-a.12.3492; 10.1109/vlsic.2005.1469369

ISSN: 17451337; 09168508

Data Source

OpenAIRE

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