Phase-error reduction technique for quadrature ring oscillators
説明
This paper proposes a quadrature ring oscillator with small phase error. The proposed technique uses two feedback loops. One of the loops calibrates phase error of two outputs while the other keeps the oscillation frequency constant. The power consumption and chip area will be reduced by the proposed technique because an additional variable delay cell is not necessary for the proposed oscillator. Effectiveness of the proposed circuit is confirmed through simulation results.
収録刊行物
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- Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.
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Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. 3 189-192, 2006-10-11
IEEE
