<title>Compiler for a dynamically reconfigurable processor with cell-array structures</title>
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ABSTRACT Our processor is featured by the architecture such that the configuration can be dynamically and optimally rearranged inreal-time. We have already developed the instruction sets, the emulation and debug programs for the present processor,utilizing circuit designs. Thispaper described a newlydeveloped compiler asthealternativetothatusingthecircuitdesigns.Keywords: Reconfigurable architecture, Parallel Processor, Pipeline Processing, Compiler, development tools 1. INTRODUCTION We had been developed the reconfigurable Cell-Array processor that realizes very high-speed parallel computations. Thisprocessor is featured by the architecture to be able to be dynamically and optimally rearranged in real-time. This processorscharacteristics are following. 8bit-processing element.On usual reconfigurable hardware, configurable devices were considered to apply to several applications. However, sinceinformation-capacity for configuration is increasing, it was difficult to use for general-purpose processors. This processorprovides the fine-grained for general-purpose processors in order to reduce information-capacityfor configuration. Limited functions.The reconfigurable architecture to realize several functions by using some elements was complex structures. Our processorprovides only four kinds of the element for general purpose computing. Each element has each limited functions. As aresult, reconfigurable system is composed simplystructure.In the first, our aim is architectures that be structured for simply instructions on the basis of the rules rather than freely. As aresult, reconfigurable process of our processor is clearlyin comparison with usual reconfigurable hardware.Our Cell-Array Processor contains four kinds of element ofmacro-Cell unit. (Figure 1) Four elements are four functionsof general purpose computing. First element is to be usedarithmetical calculation, shift and rotation, called PCA:processing cell array. Second element executes logicalcalculations (AND, OR, NOT and ExOR) as conditionalbranch, loop process and bit operation, called LCA: logic cellarray. Third element is called MCA: memory cell array,realize a space to keep values for calculation and a delay time.Last element is CCA: counter cell array, synchronize eachCell-Array. And, this processor includes the bus to connectCell-Arrays and bus-switches to control data streams.F igure 1: Four Elements
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- SPIE Proceedings
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SPIE Proceedings 4212 96-103, 2000-10-06
SPIE