An architecture for compact associative memories with deca-ns nearest-match capability up to large distances
説明
Associative-memory architecture for Hamming-distance search, compact implementation, and short nearest-matches times up to large distances are proposed. The main ideas are fast analog word comparison and self-adaptive winner-line-up amplification. An implementation in a 0.6 /spl mu/m 2-poly 3-metal CMOS technology with 32 rows and 128 columns verifies the key concepts. Search time is <38 ns.
収録刊行物
-
- 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
-
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) 170-171,, 2002-11-13
IEEE
