Design methodology and system for a configurable media embedded processor extensible to VLIW architecture
説明
A new integrated system to design and generate a configurable embedded processor for multimedia applications has been developed. The system, "Media embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable embedded processor but also for its template based extensible VLIW co-processor. This paper describes the architecture and the function of the "Media embedded Processor Integrator" especially focusing on how the system treats the VLIW co-processor extension. In order to determine an ISA for a 3-way VLIW co-processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.
収録刊行物
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- Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors
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Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors 2-7, 2003-06-26
IEEE Comput. Soc