A neural network accelerator using matrix memory with broadcast bus
説明
A parallel processing architecture utilizing matrix memory is proposed. Significant improvement of weight updating speed has been achieved for neural network simulations. The proposed system is expandible, fast and within an acceptable performance/cost. Simulating BP on the system is shown and comparisons are made with several other well known systems.
収録刊行物
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- Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan)
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Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan) 3 3050-3053, 2005-08-24
IEEE