A framework of evolutionary graph generation system and its application to circuit synthesis
説明
This paper presents a generic object-oriented framework of evolutionary graph generation (EGG) for automated arithmetic circuit synthesis. The EGG system can be systematically modified for different design problems by inheriting the framework class templates. The potential of the framework is examined through experimental synthesis of bit-serial arithmetic circuits.
収録刊行物
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- Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
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Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. 5 V-201, 2003-11-04
IEEE
