Yield-centric layout optimization with precise quantification of lithographic yield loss

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ABSTRACT Continuous shrinkage of the design rule in LSI devices brings about greater difficulty in the manufacturing process. Since not only process engineers’ efforts but also yield-centric layout optimization is becoming increasingly important, such optimization has recently become a focus of interest. One of the approached is lithographic hotspot modification in design data 1-5) . Using lithography compliance check and a hotspot fixing system in the early stage of design, design with wider process margin can be obtained. In order to achieve higher process yield after hotspot fixing, layout should be carefully optimized to decrease pattern- dependent yield loss. Since yield value for the design will fluc tuate sensitively as designed pattern are modified, pattern should be optimized based on a comprehensive consideration of yield loss covering parametric, systematic and random effects. In this work, using lithography simulation, a lithographic yield loss model is defined 6)

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