Jitter estimation methodology for clock chips
説明
A simulation methodology is developed for clock chips to predict their AC performance more accurately. Power bus modeling is shown to lead to more accurate and predictable jitter values. Jitter variation is plotted for a typical set of 2CPU-7PCI simultaneously switching pads, for the variation in inductance, capacitive load and frequency.
収録刊行物
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- VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
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VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design 480-483, 2002-11-07
IEEE Comput. Soc