Design of nanoelectronic ICs: Noise-tolerant logic based on cyclic BDD
説明
This paper reports new and practical design schemes for nanoscale integrated circuits, in order to ensure their functionality despite noise and faults. The proposed designs use a new cyclic binary decision diagram (BDD). The cyclic BDD enables the conventional BDD design algorithms by using feedback and Markov Random Field (MRF) model of logic gates. By applying the feedback and MRF premises, effective and robust design can be achieved. Simulations are reported to justify the fault-tolerance and noise-immunity of the proposed schemes.
収録刊行物
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- 2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO)
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2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO) 1-5, 2012-08-01
IEEE