Preventing timing errors on register writes
書誌事項
- タイトル別名
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- mechanisms of detections and recoveries
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説明
<jats:p>To deal with the increasing varitations of the intra-chip transisters, one promising approach is to dynamically detect and recover the timing-errors with microarchitecutre. This will induce dependability and efficiency into microprocessors because it allows VLSI to operate at the optimum frequency and voltage while ensuring accuracy.</jats:p> <jats:p>A few approaches for dynamically detecting timing-errors have been proposed, but none of them have focused on register writes. In this paper, we propose a technique for detecting and recovering from timing errors during register writes. We introduce a verifying technique that uses additional buffer (called the write assurance buffer (WAB)) which is provided with a sufficient timing margin. The evaluation results reveal a performance degradation of 4.5% using an 8-entry WAB; this value becomes negligible when a 16-entry WAB is used.</jats:p>
収録刊行物
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- ACM SIGARCH Computer Architecture News
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ACM SIGARCH Computer Architecture News 35 25-31, 2007-12-01
Association for Computing Machinery (ACM)
