Physical origin of pFET threshold voltage modulation by Ge channel ion implantation (GC-I/I)
説明
We show a new Ge channel ion implantation scheme for realization of low-V TH pFET, which enables ∼500mV V TH lowering with no T inv , GIDL and NBTI degradations. We also reveal the physical origin of the large V TH modulation. Based on experimental findings, we propose simplified photo-resist masked dual low-V TH CMOS flow and demonstrate low-V TH pFET/nFET operations.
収録刊行物
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- 2010 International Electron Devices Meeting
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2010 International Electron Devices Meeting 11.4.1-11.4.4, 2010-12-01
IEEE