A field-programmable digital filter chip using multiple-valued current-mode logic
説明
This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The prototype FPDF fabrication with 0.6 /spl mu/m CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 74%, respectively, compared with the standard binary logic implementation.
収録刊行物
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- 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.
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33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. 213-220, 2004-06-22
IEEE