Clock-feedthrough compensated sample/hold circuits
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説明
A novel circuit technique is presented to eliminate the clock feedthrough effect in a sample/hold circuit. The device requirement is minimal, and thus it is quite useful for CMOS monolithic implementation of precise sampled analogue signal processing circuits. Experimental waveforms are also given to demonstrate its validity.
収録刊行物
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- Electronics Letters
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Electronics Letters 24 1226-1228, 1988-09-15
Institution of Engineering and Technology (IET)