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A compaction method for full chip VLSI layouts
Description
An algorithm independent layout compaction method for full chip layouts is proposed. The partitioning compaction method cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout. A 16-bit CPU core (28.8K transistors) layout was compacted on a standard workstation using this method. Both the computer memory usage and processing time were reduced. Parallel processing is possible to further speed up the computation.
Journal
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- Proceedings of the 30th international on Design automation conference - DAC '93
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Proceedings of the 30th international on Design automation conference - DAC '93 407-412, 1993-01-01
ACM Press