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30-ns 55-b shared radix 2 division and square root using a self-timed circuit
Description
A shared radix 2 division and square root implementation using a self-timed circuit is presented. The same execution time for division and square root is achieved by using an on-the-fly digit decoding and a root multiple generation technique. Most of the hardware is shared, and only several multiplexers are required to exchange a divisor multiple and a root multiple. Moreover, quotient selection logic is accelerated by a new algorithm using a 3-b carry propagation adder. The implementation of the shared division and square root unit is realized by assuming 0.3 /spl mu/m CMOS technology. The wiring capacitance and other parasitic parameters are taken into account. The execution time of floating point 55-b full mantissa division and square root is expected to be less than 30 ns in the worst case of an input vector determined by an intensive circuit simulation. >
Journal
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- Proceedings of the 12th Symposium on Computer Arithmetic
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Proceedings of the 12th Symposium on Computer Arithmetic 98-105, 2002-11-19
IEEE Comput. Soc. Press