4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control

Multiphase DC-DC converters are essential to provide good efficiency over a wide range of load current, especially for today's multicore SoCs, which usually have a wide range of current profile. Active-phase-count (APC) control, as proposed in [1-3], is the key technique that offers the wide load range, and dynamically adjusts the number of phases according to load conditions. However, an APC transition induces a voltage disturbance due to current redistribution among phases. This makes the APC control only suitable for a voltage regulator with large output capacitors beyond 1000μF, or with high switching frequency beyond 10MHz [4] that hardly delivers more than 2A current with a good efficiency. To mitigate the disturbance impact, [2] has proposed adding or dropping a phase slowly, to allow the PID control to gradually redistribute the phase currents. However, the load current may change direction spontaneously before the completion of the transition, leading to deterioration in the transient response. This paper presents a fast APC scheme which performs the transition within 1 switching cycle, and only requires 66μF capacitors to limit the voltage ripple within 10mV, an 88% ripple reduction with respect to the optimal PID-only control. The proposed APC scheme utilizes digital phase current data, which is also needed to determine the optimal phase count [1-3]. However, the A/D conversions consume 3mW, which is 28% of the total power consumption. A continuous-time/discrete-time (CT/DT) hybrid current control architecture is introduced to eliminate the 3mW penalty while producing A/D converted data by time sharing of the analog circuitry in the control loop. Moreover, a fast transient response configuration is designed, offering less than 40mV fluctuation during an 8A load transition and less than 5mV fluctuation during a 2V line transition.