IDDQ testability of flip-flop structures
説明
We describe IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, five kinds of master-slave D-type flip-flops are used as the circuit under test. Target faults are bridging faults. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that faults in some flip-flops cannot be detected by IDDQ testing, and this problem depends on the flip-flop structure. Performances of fully IDDQ testable flip-flops are also examined.
収録刊行物
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- Digest of Papers 1996 IEEE International Workshop on IDDQ Testing
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Digest of Papers 1996 IEEE International Workshop on IDDQ Testing 29-33, 2002-12-23
IEEE Comput. Soc. Press
